View MB84VD23280EA_1820279.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-50211-1e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & sram cmos 64m ( 8/ 16) flash memory & 8m ( 8/ 16) static ram MB84VD23280EA -90 /mb84vd23280ee -90 n features ? power supply voltage of 2.7 v to 3.3 v ? high performance 90 ns maximum access time (flash) 70 ns maximum access time (sram) ? operating temperature C25 c to +85 c ? package 101-ball bga (continued) n product lineup n pac k ag e flash memory sram ordering part no. v cc f, v cc s = 3.0 v MB84VD23280EA-90/mb84vd23280ee-90 max. address access time (ns) 90 70 max. ce access time (ns) 90 70 max. oe access time (ns) 35 35 101-pin plastic fbga bga-101p-m01 +0.3v C0.3 v
MB84VD23280EA-90/mb84vd23280ee-90 2 (continued) flash memory ? simultaneous read/write operations (flex bank) two virtual banks are chosen from the combination of four physical banks host system can program or erase in one bank, then read immediately and simultaneously read from the other bank between read and write operations read-while-erase read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture sixteen 4 k words and one hundred twenty-six 32 k word. any combination of sectors can be concurrently erased. also supports full chip erase. ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? hidden rom (hi-rom) region 256 byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of 2 of 8 kbytes on both ends of each boot sector, regardless of sector protection/ unprotection status. at v ih , allows removal of boot sector protection at v acc , increases program performance ? program suspend/resume suspends the program operation to allow a read in another address ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? please refer to mbm29dl640e data sheet in detailed function sram ? power dissipation operating : 50 ma max. standby : 25 m a max. ? power down features using ce1 s and ce2s ? data retention supply voltage: 1.5 v to 3.3 v ?ce1 s and ce2s chip select ? byte data control: lb s (dq 7 -dq 0 ), ub s (dq 15 -dq 8 ) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
MB84VD23280EA-90/mb84vd23280ee-90 3 n pin assignment (bga-101p-m01) marking side (top view) dq 8 dq 2 dq 11 dq 14 n.c. n.c. n.c. n.c. n.c. n.c. n.c. cios n.c. ce2s n.c. n.c. d9 d8 d7 d6 d5 c7 c6 e9 e8 e7 e6 f9 f8 f7 f6 g9 g8 g5 h9 h8 h5 j9 j8 j7 j6 k9 k8 k7 k6 l9 l8 l7 l6 e5 f5 j5 k5 l5 d4 g4 h4 e4 f4 j4 k4 l4 g3 h3 g2 h2 e3 f3 j3 k3 m7 m6 a 11 lbs wp/acc we a 7 d2 a 12 e10 f10 g10 h10 j10 k10 a 15 a 3 ubs reset a 6 a 13 a 20 a 2 a 18 ry/by a 21 a 5 a 14 a 1 a 17 n.c. g11 c11 b11 a11 n.c. a10 b10 c10 n.c. n.c. n.c. a12 b12 c12 n.c. n.c. n.c. n.c. n.c. n.c. n.c. c2 b2 a2 a1 b1 c1 n.c. n.c. n.c. a3 b3 c3 n.c. n.c. n.c. n.c. n.c. n.c. p2 n2 m2 m1 n1 p1 n.c. n.c. n.c. m3 n3 p3 n.c. n.c. n.c. n.c. n.c. n.c. p11 n11 m11 m10 n10 p10 n.c. n.c. n.c. m12 n12 p12 n.c. a 4 sa a 16 a 0 dq 1 n.c. h11 n.c. vss dq 10 vccf vccs dq 7 dq 15 /a -1 dq 5 a 8 a 19 a 9 a 10 dq 6 dq 12 dq 13 vss ce1s dq 0 cef dq 4 dq 3 dq 9 ciof oe
MB84VD23280EA-90/mb84vd23280ee-90 4 n n n n pin description pin name input/ output description a 18 to a 0 i address inputs (common) a 21 to a 19 , a C1 i address inputs (flash) sa i address input (sram) dq 15 to dq 0 i/o data inputs/outputs (common) ce f i chip enable (flash) ce1 s i chip enable (sram) ce2s i chip enable (sram) oe i output enable (common) we i write enable (common) ry/by o ready/busy output (flash) open drain output ub s i upper byte control (sram) lb s i lower byte control (sram) ciof i i/o configuration (flash) ciof = v ih is word mode (16), ciof = v il is byte mode (8) cios i i/o configuration (sram) cios = v ih is word mode (16), cios = v il is byte mode (8) reset i hardware reset pin/sector protection unlock (flash) wp /acc i write protect / acceleration (flash) n.c. no internal connection v ss power device ground (common) v cc f power device power supply (flash) v cc s power device power supply (sram)
MB84VD23280EA-90/mb84vd23280ee-90 5 n block diagram v ss v cc s 64 m bit reset flash memory we 8 m bit static ram ce f a 21 to a 0 oe ce1 s v ss v cc f a 21 to a 0 a 18 to a 0 dq 15 /a C 1 to dq 0 ry/by lb s ub s ciof wp /acc ce2s dq 15 /a C 1 to dq 0 dq 15 to dq 0 a C1 sa cios
MB84VD23280EA-90/mb84vd23280ee-90 6 n n n n device bus operations table 1. 1 user bus operations (flash = word mode; ciof = v cc f, sram = word mode; cios = v cc s) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except for indicated this column are inhibited. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 3. do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. 4. it is also used for the extended sector group protections. 5. protect of 2 of 8 kbytes on both ends of each boot sector. 6. sa; dont care or open. operation (1), (3) ce fce1 sce2s oe we sa (6) lb sub sdq 7 to dq 0 dq 15 to dq 8 reset wp / acc (5) full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash (2) l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h x ll d out d out hx hl high-z d out lh d out high-z write to sram h l h x l x ll d in d in hx hl high-z d in lh d in high-z temporary sector group unprotection(4) x x x xxxxx x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection x x x xxxxx x x x l
MB84VD23280EA-90/mb84vd23280ee-90 7 table 1. 2 user bus operations (flash = word mode; ciof = v cc f, sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except for indicated this column are inhibited. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 3. do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. 4. it is also used for the extended sector group protections. 5. protect of 2 of 8 kbytes on both ends of each boot sector. 6. lb s , ub s ; dont care or open. operation (1), (3) ce fce1 sce2s oe we sa lb s (6) ub s (6) dq 7 to dq 0 dq 15 to dq 8 reset wp / acc (5) full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x x x high-z high-z l hx h h x x x high-z high-z xl read from flash (2) l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector group unprotection(4) x x x xxxxx x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection x x x xxxxx x x x l
MB84VD23280EA-90/mb84vd23280ee-90 8 table 1. 3 user bus operations (flash = byte mode; ciof = v ss , sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. notes: 1. other operations except for indicated this column are inhibited. 2. we can be v il if oe is v il , oe at v ih initiates the write operations. 3. do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. 4. it is also used for the extended sector group protections. 5. protect of 2 of 8 kbytes on both ends of each boot sector. 6. lb s , ub s ; dont care or open. operation (1), (3) ce fce1 sce2sdq 15 /a C 1 oe we sa lb s (6) ub s (6) dq 7 to dq 0 dq 14 to dq 8 reset wp / acc (5) full standby h hx x x x x x x high-z high-z h x xl output disable hl h x h h x x x high-z high-z hx x x x x x x high-z high-z l hx a C1 h h x x x high-z high-z xl read from flash (2) l hx a C1 lhx x x d out xhx xl write to flash l hx a C1 hlx x x d in xhx xl read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector group unprotection(4) x x x x xxx x x x x v id x flash hardware reset x hx x x x x x x high-z high-z l x xl boot block sector write protection x x x x xxx x x x x x l
MB84VD23280EA-90/mb84vd23280ee-90 9 n n n n flexible sector-erase architecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. MB84VD23280EA/ee sector architecture sa31 : 64kb (32kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 8kb (4kw) sa6 : 8kb (4kw) sa5 : 8kb (4kw) sa4 : 8kb (4kw) sa3 : 8kb (4kw) sa2 : 8kb (4kw) sa70 : 64kb (32kw) sa69 : 64kb (32kw) sa68 : 64kb (32kw) sa67 : 64kb (32kw) sa66 : 64kb (32kw) sa65 : 64kb (32kw) sa64 : 64kb (32kw) sa63 : 64kb (32kw) sa62 : 64kb (32kw) sa61 : 64kb (32kw) sa60 : 64kb (32kw) sa59 : 64kb (32kw) sa58 : 64kb (32kw) sa57 : 64kb (32kw) sa56 : 64kb (32kw) sa55 : 64kb (32kw) sa54 : 64kb (32kw) sa53 : 64kb (32kw) sa52 : 64kb (32kw) sa51 : 64kb (32kw) sa50 : 64kb (32kw) sa49 : 64kb (32kw) sa48 : 64kb (32kw) sa47 : 64kb (32kw) sa46 : 64kb (32kw) sa45 : 64kb (32kw) sa44 : 64kb (32kw) sa43 : 64kb (32kw) sa42 : 64kb (32kw) sa41 : 64kb (32kw) sa40 : 64kb (32kw) sa39 : 64kb (32kw) sa38 : 64kb (32kw) sa37 : 64kb (32kw) sa36 : 64kb (32kw) sa35 : 64kb (32kw) sa34 : 64kb (32kw) sa33 : 64kb (32kw) sa32 : 64kb (32kw) sa1 : 8kb (4kw) sa0 : 8kb (4kw) bank a bank b 070000h 078000h 060000h 068000h 050000h 058000h 040000h 048000h 030000h 038000h 020000h 028000h 010000h 018000h 007000h 008000h 005000h 006000h 003000h 004000h 001000h 002000h 000000h sa102 : 64kb (32kw) sa101 : 64kb (32kw) sa100 : 64kb (32kw) sa99 : 64kb (32kw) sa98 : 64kb (32kw) sa97 : 64kb (32kw) sa96 : 64kb (32kw) sa95 : 64kb (32kw) sa94 : 64kb (32kw) sa93 : 64kb (32kw) sa92 : 64kb (32kw) sa91 : 64kb (32kw) sa90 : 64kb (32kw) sa89 : 64kb (32kw) sa88 : 64kb (32kw) sa87 : 64kb (32kw) sa86 : 64kb (32kw) sa85 : 64kb (32kw) sa84 : 64kb (32kw) sa83 : 64kb (32kw) sa82 : 64kb (32kw) sa81 : 64kb (32kw) sa80 : 64kb (32kw) sa79 : 64kb (32kw) sa78 : 64kb (32kw) sa77 : 64kb (32kw) sa76 : 64kb (32kw) sa75 : 64kb (32kw) sa74 : 64kb (32kw) sa73 : 64kb (32kw) 3fffffh sa141 : 8kb (4kw) sa140 : 8kb (4kw) sa139 : 8kb (4kw) sa138 : 8kb (4kw) sa137 : 8kb (4kw) sa136 : 8kb (4kw) sa135 : 8kb (4kw) sa134 : 8kb (4kw) sa133 : 64kb (32kw) sa132 : 64kb (32kw) sa131 : 64kb (32kw) sa130 : 64kb (32kw) sa129 : 64kb (32kw) sa128 : 64kb (32kw) sa127 : 64kb (32kw) sa126 : 64kb (32kw) sa125 : 64kb (32kw) sa124 : 64kb (32kw) sa123 : 64kb (32kw) sa122 : 64kb (32kw) sa121 : 64kb (32kw) sa120 : 64kb (32kw) sa119 : 64kb (32kw) sa118 : 64kb (32kw) sa117 : 64kb (32kw) sa116 : 64kb (32kw) sa115 : 64kb (32kw) sa114 : 64kb (32kw) sa113 : 64kb (32kw) sa112 : 64kb (32kw) sa111 : 64kb (32kw) sa110 : 64kb (32kw) sa109 : 64kb (32kw) sa108 : 64kb (32kw) sa107 : 64kb (32kw) sa106 : 64kb (32kw) sa105 : 64kb (32kw) sa104 : 64kb (32kw) sa103 : 64kb (32kw) sa72 : 64kb (32kw) sa71 : 64kb (32kw) bank c bank d 3ff000h 3fe000h 3fd000h 3fc000h 3fb000h 3fa000h 3f9000h 0f0000h 0f8000h 0e0000h 0e8000h 0d0000h 0d8000h 0c0000h 0c8000h 0b0000h 0b8000h 0a0000h 0a8000h 090000h 098000h 088000h 080000h 170000h 178000h 160000h 168000h 150000h 158000h 140000h 148000h 130000h 138000h 120000h 128000h 110000h 118000h 100000h 108000h 1f0000h 1f8000h 1e0000h 1e8000h 1d0000h 1d8000h 1c0000h 1c8000h 1b0000h 1b8000h 1a0000h 1a8000h 190000h 198000h 188000h 180000h 270000h 278000h 260000h 268000h 250000h 258000h 240000h 248000h 230000h 238000h 220000h 228000h 210000h 218000h 208000h 2f0000h 2f8000h 2e0000h 2e8000h 2d0000h 2d8000h 2c0000h 2c8000h 2b0000h 2b8000h 2a0000h 2a8000h 290000h 298000h 288000h 280000h 370000h 378000h 360000h 368000h 350000h 358000h 340000h 348000h 330000h 338000h 320000h 328000h 310000h 318000h 300000h 308000h 3f0000h 3f8000h 3e0000h 3e8000h 3d0000h 3d8000h 3c0000h 3c8000h 3b0000h 3b8000h 3a0000h 3a8000h 390000h 398000h 388000h 380000h 200000h 1fffffh 0e0000h 0f0000h 0c0000h 0d0000h 0a0000h 0b0000h 080000h 090000h 060000h 070000h 040000h 050000h 020000h 030000h 00e000h 010000h 00a000h 00c000h 006000h 008000h 002000h 004000h 000000h 1e0000h 1f0000h 1c0000h 1d0000h 1a0000h 1b0000h 180000h 190000h 160000h 170000h 140000h 158000h 120000h 130000h 110000h 100000h 2e0000h 2f0000h 2c0000h 2d0000h 2a0000h 2b0000h 280000h 290000h 260000h 270000h 240000h 250000h 220000h 230000h 200000h 210000h 3e0000h 3f0000h 3c0000h 3d0000h 3a0000h 3b0000h 380000h 390000h 360000h 370000h 340000h 350000h 320000h 330000h 310000h 300000h 3fffffh word mode byte mode word mode byte mode 7fffffh 7fe000h 7fc000h 7fa000h 7f8000h 7f6000h 7f4000h 7f2000h 4e0000h 4f0000h 4c0000h 4d0000h 4a0000h 4b0000h 480000h 490000h 460000h 470000h 440000h 450000h 420000h 430000h 410000h 5e0000h 5f0000h 5c0000h 5d0000h 5a0000h 5b0000h 580000h 590000h 560000h 570000h 540000h 550000h 520000h 530000h 510000h 500000h 6e0000h 6f0000h 6c0000h 6d0000h 6a0000h 6b0000h 680000h 690000h 660000h 670000h 640000h 650000h 620000h 630000h 600000h 610000h 7e0000h 7f0000h 7c0000h 7d0000h 7a0000h 7b0000h 780000h 790000h 760000h 770000h 740000h 750000h 720000h 730000h 710000h 700000h 400000h
MB84VD23280EA-90/mb84vd23280ee-90 10 table 2 example of virtual banks combination banka: address 000000h to 07ffffh (word) , 000000h to 0fffffh (byte) bankb: address 080000h to 1fffffh (word) , 100000h to 3fffffh (byte) bankc: address 200000h to 37ffffh (word) , 400000h to 6fffffh (byte) bankd: address 380000h to 3fffffh (word) , 700000h to 7fffffh (byte) table 3 sector address tables (continued) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 1 8m bit bank a 8 of 8 kbyte / 4 k word + 15 of 64 kbyte / 32 k word 56 mbit bank b + bank c + bank d 8 of 8 kbyte / 4 k word + 111 of 64 kbyte / 32 k word 216 mbit bank a + bank d 16 of 8 kbyte / 4 k word + 30 of 64 kbyte / 32 k word 48 mbit bank b + bank c 96 of 64 kbyte / 32 k word 3 24 mbit bank b 48 of 64 kbyte / 32 k word 40 mbit bank a + bank c + bank d 16 of 8 kbyte / 4 k word + 78 of 64 kbyte / 32 k word 432 mbit bank a + bank b 8 of 8 kbyte / 4 k word + 63 of 64 kbyte / 32 k word 32 mbit bank c + bank d 8 of 8 kbyte / 4 k word + 63 of 64 kbyte / 32 k word bank sector sector address address range bank address byte mode word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0 0 0 0 0 0 0 0 0 0 000000h to 001fffh 000000h to 000fffh sa1 0 0 0 0 0 0 0 0 0 1 002000h to 003fffh 001000h to 001fffh sa2 0 0 0 0 0 0 0 0 1 0 004000h to 005fffh 002000h to 002fffh sa3 0 0 0 0 0 0 0 0 1 1 006000h to 007fffh 003000h to 003fffh sa4 0 0 0 0 0 0 0 1 0 0 008000h to 009fffh 004000h to 004fffh sa5 0 0 0 0 0 0 0 1 0 1 00a000h to 00bfffh 005000h to 005fffh sa6 0 0 0 0 0 0 0 1 1 0 00c000h to 00dfffh 006000h to 006fffh sa7 0 0 0 0 0 0 0 1 1 1 00e000h to 00ffffh 007000h to 007fffh sa8 0 0 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa9 0 0 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa10 0 0 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa11 0 0 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa12 0 0 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa13 0 0 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa14 0 0 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa15 0 0 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa16 0 0 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa17 0 0 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa18 0 0 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa19 0 0 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa20 0 0 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa21 0 0 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa22 0 0 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh
MB84VD23280EA-90/mb84vd23280ee-90 11 (continued) (continued) bank sector sector address address range bank address byte mode word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa23 0 0 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa24 0 0 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa25 0 0 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa26 0 0 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa27 0 0 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa28 0 0 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa29 0 0 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa30 0 0 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa31 0 0 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa32 0 0 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa33 0 0 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa34 0 0 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa35 0 0 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa36 0 0 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa37 0 0 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa38 0 0 1 1 1 1 1 x x x 1f0000h to 1fffffh 0f8000h to 0fffffh sa39 0 1 0 0 0 0 0 x x x 200000h to 20ffffh 100000h to 107fffh sa40 0 1 0 0 0 0 1 x x x 210000h to 21ffffh 108000h to 10ffffh sa41 0 1 0 0 0 1 0 x x x 220000h to 22ffffh 110000h to 117fffh sa42 0 1 0 0 0 1 1 x x x 230000h to 23ffffh 118000h to 11ffffh sa43 0 1 0 0 1 0 0 x x x 240000h to 24ffffh 120000h to 127fffh sa44 0 1 0 0 1 0 1 x x x 250000h to 25ffffh 128000h to 12ffffh sa45 0 1 0 0 1 1 0 x x x 260000h to 26ffffh 130000h to 137fffh sa46 0 1 0 0 1 1 1 x x x 270000h to 27ffffh 138000h to 13ffffh sa47 0 1 0 1 0 0 0 x x x 280000h to 28ffffh 140000h to 147fffh sa48 0 1 0 1 0 0 1 x x x 290000h to 29ffffh 148000h to 14ffffh sa49 0 1 0 1 0 1 0 x x x 2a0000h to 2affffh 150000h to 157fffh sa50 0 1 0 1 0 1 1 x x x 2b0000h to 2bffffh 158000h to 15ffffh sa51 0 1 0 1 1 0 0 x x x 2c0000h to 2cffffh 160000h to 167fffh sa52 0 1 0 1 1 0 1 x x x 2d0000h to 2dffffh 168000h to 16ffffh sa53 0 1 0 1 1 1 0 x x x 2e0000h to 2effffh 170000h to 177fffh sa54 0 1 0 1 1 1 1 x x x 2f0000h to 2fffffh 178000h to 17ffffh sa55 0 1 1 0 0 0 0 x x x 300000h to 30ffffh 180000h to 187fffh sa56 0 1 1 0 0 0 1 x x x 310000h to 31ffffh 188000h to 18ffffh sa57 0 1 1 0 0 1 0 x x x 320000h to 32ffffh 190000h to 197fffh sa58 0 1 1 0 0 1 1 x x x 330000h to 33ffffh 198000h to 19ffffh sa59 0 1 1 0 1 0 0 x x x 340000h to 34ffffh 1a0000h to 1a7fffh sa60 0 1 1 0 1 0 1 x x x 350000h to 35ffffh 1a8000h to 1affffh sa61 0 1 1 0 1 1 0 x x x 360000h to 36ffffh 1b0000h to 1b7fffh sa62 0 1 1 0 1 1 1 x x x 370000h to 37ffffh 1b8000h to 1bffffh sa63 0 1 1 1 0 0 0 x x x 380000h to 38ffffh 1c0000h to 1c7fffh sa64 0 1 1 1 0 0 1 x x x 390000h to 39ffffh 1c8000h to 1cffffh sa65 0 1 1 1 0 1 0 x x x 3a0000h to 3affffh 1d0000h to 1d7fffh sa66 0 1 1 1 0 1 1 x x x 3b0000h to 3bffffh 1d8000h to 1dffffh sa67 0 1 1 1 1 0 0 x x x 3c0000h to 3cffffh 1e0000h to 1e7fffh sa68 0 1 1 1 1 0 1 x x x 3d0000h to 3dffffh 1e8000h to 1effffh sa69 0 1 1 1 1 1 0 x x x 3e0000h to 3effffh 1f0000h to 1f7fffh sa70 0 1 1 1 1 1 1 x x x 3f0000h to 3fffffh 1f8000h to 1fffffh
MB84VD23280EA-90/mb84vd23280ee-90 12 (continued) (continued) bank sector sector address address range bank address byte mode word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa71 1 0 0 0 0 0 0 x x x 400000h to 40ffffh 200000h to 207fffh sa72 1 0 0 0 0 0 1 x x x 410000h to 41ffffh 208000h to 20ffffh sa73 1 0 0 0 0 1 0 x x x 420000h to 42ffffh 210000h to 217fffh sa74 1 0 0 0 0 1 1 x x x 430000h to 43ffffh 218000h to 21ffffh sa75 1 0 0 0 1 0 0 x x x 440000h to 44ffffh 220000h to 227fffh sa76 1 0 0 0 1 0 1 x x x 450000h to 45ffffh 228000h to 22ffffh sa77 1 0 0 0 1 1 0 x x x 460000h to 46ffffh 230000h to 237fffh sa78 1 0 0 0 1 1 1 x x x 470000h to 47ffffh 238000h to 23ffffh sa79 1 0 0 1 0 0 0 x x x 480000h to 48ffffh 240000h to 247fffh sa80 1 0 0 1 0 0 1 x x x 490000h to 49ffffh 248000h to 24ffffh sa81 1 0 0 1 0 1 0 x x x 4a0000h to 4affffh 250000h to 257fffh sa82 1 0 0 1 0 1 1 x x x 4b0000h to 4bffffh 258000h to 25ffffh sa83 1 0 0 1 1 0 0 x x x 4c0000h to 4cffffh 260000h to 267fffh sa84 1 0 0 1 1 0 1 x x x 4d0000h to 4dffffh 268000h to 26ffffh sa85 1 0 0 1 1 1 0 x x x 4e0000h to 4effffh 270000h to 277fffh sa86 1 0 0 1 1 1 1 x x x 4f0000h to 4fffffh 278000h to 27ffffh sa87 1 0 1 0 0 0 0 x x x 500000h to 50ffffh 280000h to 287fffh sa88 1 0 1 0 0 0 1 x x x 510000h to 51ffffh 288000h to 28ffffh sa89 1 0 1 0 0 1 0 x x x 520000h to 52ffffh 290000h to 297fffh sa90 1 0 1 0 0 1 1 x x x 530000h to 53ffffh 298000h to 29ffffh sa91 1 0 1 0 1 0 0 x x x 540000h to 54ffffh 2a0000h to 2a7fffh sa92 1 0 1 0 1 0 1 x x x 550000h to 55ffffh 2a8000h to 2affffh sa93 1 0 1 0 1 1 0 x x x 560000h to 56ffffh 2b0000h to 2b7fffh sa94 1 0 1 0 1 1 1 x x x 570000h to 57ffffh 2b8000h to 2bffffh sa95 1 0 1 1 0 0 0 x x x 580000h to 58ffffh 2c0000h to 2c7fffh sa96 1 0 1 1 0 0 1 x x x 590000h to 59ffffh 2c8000h to 2cffffh sa97 1 0 1 1 0 1 0 x x x 5a0000h to 5affffh 2d0000h to 2d7fffh sa98 1 0 1 1 0 1 1 x x x 5b0000h to 5bffffh 2d8000h to 2dffffh sa99 1 0 1 1 1 0 0 x x x 5c0000h to 5cffffh 2e0000h to 2e7fffh sa100 1 0 1 1 1 0 1 x x x 5d0000h to 5dffffh 2e8000h to 2effffh sa101 1 0 1 1 1 1 0 x x x 5e0000h to 5effffh 2f0000h to 2f7fffh sa102 1 0 1 1 1 1 1 x x x 5f0000h to 5fffffh 2f8000h to 2fffffh sa103 1 1 0 0 0 0 0 x x x 600000h to 60ffffh 300000h to 307fffh sa104 1 1 0 0 0 0 1 x x x 610000h to 61ffffh 308000h to 30ffffh sa105 1 1 0 0 0 1 0 x x x 620000h to 62ffffh 310000h to 317fffh sa106 1 1 0 0 0 1 1 x x x 630000h to 63ffffh 318000h to 31ffffh sa107 1 1 0 0 1 0 0 x x x 640000h to 64ffffh 320000h to 327fffh sa108 1 1 0 0 1 0 1 x x x 650000h to 65ffffh 328000h to 32ffffh sa109 1 1 0 0 1 1 0 x x x 660000h to 66ffffh 330000h to 337fffh sa110 1 1 0 0 1 1 1 x x x 670000h to 67ffffh 338000h to 33ffffh sa111 1 1 0 1 0 0 0 x x x 680000h to 68ffffh 340000h to 347fffh sa112 1 1 0 1 0 0 1 x x x 690000h to 69ffffh 348000h to 34ffffh sa113 1 1 0 1 0 1 0 x x x 6a0000h to 6affffh 350000h to 357fffh sa114 1 1 0 1 0 1 1 x x x 6b0000h to 6bffffh 358000h to 35ffffh sa115 1 1 0 1 1 0 0 x x x 6c0000h to 6cffffh 360000h to 367fffh sa116 1 1 0 1 1 0 1 x x x 6d0000h to 6dffffh 368000h to 36ffffh sa117 1 1 0 1 1 1 0 x x x 6e0000h to 6effffh 370000h to 377fffh sa118 1 1 0 1 1 1 1 x x x 6f0000h to 6fffffh 378000h to 37ffffh
MB84VD23280EA-90/mb84vd23280ee-90 13 (continued) bank sector sector address address range bank address byte mode word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa119 1 1 1 0 0 0 0 x x x 700000h to 70ffffh 380000h to 387fffh sa120 1 1 1 0 0 0 1 x x x 710000h to 71ffffh 388000h to 38ffffh sa121 1 1 1 0 0 1 0 x x x 720000h to 72ffffh 390000h to 397fffh sa122 1 1 1 0 0 1 1 x x x 730000h to 73ffffh 398000h to 39ffffh sa123 1 1 1 0 1 0 0 x x x 740000h to 74ffffh 3a0000h to 3a7fffh sa124 1 1 1 0 1 0 1 x x x 750000h to 75ffffh 3a8000h to 3affffh sa125 1 1 1 0 1 1 0 x x x 760000h to 76ffffh 3b0000h to 3b7fffh sa126 1 1 1 0 1 1 1 x x x 770000h to 77ffffh 3b8000h to 3bffffh sa127 1 1 1 1 0 0 0 x x x 780000h to 78ffffh 3c0000h to 3c7fffh sa128 1 1 1 1 0 0 1 x x x 790000h to 79ffffh 3c8000h to 3cffffh sa129 1 1 1 1 0 1 0 x x x 7a0000h to 7affffh 3d0000h to 3d7fffh sa130 1 1 1 1 0 1 1 x x x 7b0000h to 7bffffh 3d8000h to 3dffffh sa131 1 1 1 1 1 0 0 x x x 7c0000h to 7cffffh 3e0000h to 3e7fffh sa132 1 1 1 1 1 0 1 x x x 7d0000h to 7dffffh 3e8000h to 3effffh sa133 1 1 1 1 1 1 0 x x x 7e0000h to 7effffh 3f0000h to 3f7fffh sa134 1 1 1 1 1 1 1 0 0 0 7f0000h to 7f1fffh 3f8000h to 3f8fffh sa135 1 1 1 1 1 1 1 0 0 1 7f2000h to 7f3fffh 3f9000h to 3f9fffh sa136 1 1 1 1 1 1 1 0 1 0 7f4000h to 7f5fffh 3fa000h to 3fafffh sa137 1 1 1 1 1 1 1 0 1 1 7f6000h to 7f7fffh 3fb000h to 3fbfffh sa138 1 1 1 1 1 1 1 1 0 0 7f8000h to 7f9fffh 3fc000h to 3fcfffh sa139 1 1 1 1 1 1 1 1 0 1 7fa000h to 7fbfffh 3fd000h to 3fdfffh sa140 1 1 1 1 1 1 1 1 1 0 7fc000h to 7fdfffh 3fe000h to 3fefffh sa141 1 1 1 1 1 1 1 1 1 1 7fe000h to 7fffffh 3ff000h to 3fffffh
MB84VD23280EA-90/mb84vd23280ee-90 14 table 4 sector group addresses (MB84VD23280EA/ee) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 00 xxx sa8 to sa10 01 10 sga9 00001 xxxxx sa11 to sa14 sga10 00010 xxxxx sa15 to sa18 sga11 00011 xxxxx sa19 to sa22 sga12 00100 xxxxx sa23 to sa26 sga13 00101 xxxxx sa27 to sa30 sga14 00110 xxxxx sa31 to sa34 sga15 00111 xxxxx sa35 to sa38 sga16 01000 xxxxx sa39 to sa42 sga17 01001 xxxxx sa43 to sa46 sga18 01010 xxxxx sa47 to sa50 sga19 01011 xxxxx sa51 to sa54 sga20 01100 xxxxx sa55 to sa58 sga21 01101 xxxxx sa59 to sa62 sga22 01110 xxxxx sa63 to sa66 sga23 01111 xxxxx sa67 to sa70 sga24 10000 xxxxx sa71 to sa74 sga25 10001 xxxxx sa75 to sa78 sga26 10010 xxxxx sa79 to sa82 sga27 10011 xxxxx sa83 to sa86 sga28 10100 xxxxx sa87 to sa90 sga29 10101 xxxxx sa91 to sa94 sga30 10110 xxxxx sa95 to sa98 sga31 10111 xxxxx sa99 to sa102 sga32 11000 xxxxx sa103 to sa106 sga33 11001 xxxxx sa107 to sa110 sga34 11010 xxxxx sa111 to sa114 sga35 11011 xxxxx sa115 to sa118 sga36 11100 xxxxx sa119 to sa122 sga37 11101 xxxxx sa123 to sa126 sga38 11110 xxxxx sa127 to sa130 sga39 11111 00 xxx sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
MB84VD23280EA-90/mb84vd23280ee-90 15 table 5 flash memory autoselect codes *1 : a- 1 is for byte mode. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied, both bank 1 and bank 2 become autoselect mode, which leads to the simultaneous operation unable to be executed. consequently, specifying the bank address is not demanded. however, the bank address needs to be indicated when autoselect mode is read out at command mode; because then it becomes ok to activate simultaneous operation. *4 : at word mode, a read cycle at address (ba) 01h (at byte mode, (ba) 02h) outputs device code. when 227eh (at byte mode, 7eh) was output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at byte mode, (ba) 1ch) , as well as at (ba) 0fh (at byte mode, (ba) 1eh) . type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufactures code ba* 3 v il v il v il v il v il v il 04h device code byte ba* 3 v il v il v il v il v ih v il 7eh word x 227eh extended device code * 4 byte ba* 3 v il v ih v ih v ih v il v il 02h word x 2202h byte ba* 3 v il v ih v ih v ih v ih v il 01h word x 2201h sector group protection sector group addresses v il v il v il v ih v il v il 01h* 2
MB84VD23280EA-90/mb84vd23280ee-90 16 table 6 flash memory command definitions (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1 xxxh f0h byte read/reset word 3 555h aah 2aah 55h 555h f0hrard byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah program suspend 1 bab0h program resume 1 ba30h chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 bab0h erase resume 1 ba30h extended sector group protection * 2 word 4 xxxh 60h spa 60h spa 40h spa sd byte set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program * 1 word 2 xxxh a0hpapd byte xxxh reset from fast mode * 1 word 2 ba 90h xxxh * 4 f0h byte ba xxxh query word 1 (ba) 55h 98h byte (ba) aah hi-rom entry word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hi-rom program * 3 word 4 555h aah 2aah 55h 555h a0h (hra ) pa pd byte aaah 555h aaah hi-rom exit * 3 word 4 555h aah 2aah 55h (hrba ) 555h 90hxxxh00h byte aaah 555h (hrba ) aaah
MB84VD23280EA-90/mb84vd23280ee-90 17 (continued) *1: this command is valid while fast mode. *2: this command is valid while reset = v id . *3: this command is valid while hi-rom mode. *4: the data 00h is also acceptable. notes: 1. address bits a 21 to a 11 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba), and sector group address (spa). 2. bus operations are defined in tables 3 and 4. 3. ra =address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 21 , a 20 , a 19 ) 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5. spa =sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. hra = address of the hi-rom area word mode:000000h to 00007fh byte mode:000000h to 0000ffh 7. hrba = bank address of the hi-rom area (a 21 = a 20 = a 19 = v il ) 8. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 10 to a 0 byte mode: aaah or 555h to addresses a 10 to a 0 , and a -1 9. both read/reset commands are functionally equivalent, resetting the device to the read mode.
MB84VD23280EA-90/mb84vd23280ee-90 18 n n n n absolute maximum ratings *1 minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f + 0.3 v or v cc s + 0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f + 2.0 v or v cc s + 2.0 v for periods of up to 20 ns. *2: minimum dc input voltage on a 9 and oe pin is C0.3 v. minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, a 9 , oe , and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-v cc f or v cc s) does not exceed +9.0 v. maximum dc input voltage on a 9 , oe , and reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. storage temperature tstg C55 +125 c ambient temperature with power applied ta C25 +85 c voltage with respect to ground all pins except a 9 ,oe ,reset ,wp /acc * 1 v in , v out C0.3 v cc f +0.3 v v cc s +0.3 v v cc f/v cc s supply * 1 v cc f, v cc s C0.3 +4.0 v a 9 and oe * 2 v in C0.3 + 13.0 v reset * 2 v in C0.5 + 13.0 v wp /acc * 3 v in C0.5 +10.5 v parameter symbol value unit min. max. ambient temperature ta C25 +85 c v cc f/v cc s supply voltages v cc f, v cc s +2.7 +3.3 v
MB84VD23280EA-90/mb84vd23280ee-90 19 n n n n electrical characterristics 1. dc characteristics (continued) parameter symbol conditions value unit min. typ. max. input leakage current i li v in = v ss to v cc f, v cc s C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc f, v cc s C1.0 +1.0 m a reset inputs leakage current i lit v cc f = v cc f max., v cc s = v cc s max., reset = 12.5 v 35 a a cc input leakage current i lia v cc f = v cc f max., v cc s = v cc s max., wp /a cc = v acc max. 20ma flash v cc active current (read) * 1 i cc1 f ce f = v il , oe = v ih t cycle = 5 mhz byte 16 ma t cycle = 5 mhz word 18 t cycle = 1 mhz byte 7 ma t cycle = 1 mhz word 7 flash v cc active current (program/erase) * 2 i cc2 fce f = v il , oe = v ih 35ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih byte 51 ma word 53 flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih byte 51 ma word 53 flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih 35ma sram v cc active current i cc1 s v cc s = v cc max., ce1 s = v il , ce2s = v ih t cycle =10 mhz 50 ma sram v cc active current i cc2 s ce1 s = 0.2 v, ce2s = v cc s C 0.2 v t cycle = 10 mhz 50 ma t cycle = 1 mhz 10 ma flash v cc standby current i sb1 f v cc f = v cc f max., ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /a cc = v cc f 0.3 v 5 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc f max., reset = v ss 0.3 v, wp /a cc = v cc f 0.3 v 5 m a flash v cc current (auto- matic sleep mode) * 3 i sb3 f v cc f = v cc f max., ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /a cc = v cc f 0.3 v, v in = v cc f 0.3 v or v ss 0.3 v 5 m a sram v cc standby current i sb1 sce1 s > v cc s C 0.2 v, ce2s > v cc s C 0.2 v 25 m a sram v cc standby current i sb2 sce2s < 0.2v 25 m a
MB84VD23280EA-90/mb84vd23280ee-90 20 (continued) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc f applying. *5: embedded alogorithm (program or erase) is in progress. (@5 mhz) *6: v cc indicates lower of v cc f or v cc s. parameter symbol conditions value unit min. typ. max. input low level v il C0.30.5v input high level v ih 2.4 v cc +0.3 * 6 v voltage for sector protection, and temporary sector unpro- tection (reset ) * 4 v id 11.5 12.5 v voltage for program acceleration (wp /acc) * 4 v acc 8.5 9.0 9.5 v output low voltage level v ol v cc f = v cc f min., i ol =4.0 ma flash 0.45 v v cc s = v cc s min., i ol =1.0 ma sram 0.4 v output high voltage level v oh v cc f = v cc f min., i oh =C0.1 ma flash v cc fC 0.4 v v cc s = v cc s min., i oh =C0.5 ma sram 2.2 v flash low v cc f lock-out voltage v lko 2.3 2.5 v
MB84VD23280EA-90/mb84vd23280ee-90 21 2. ac characteristics ?ce timing ? timing diagram for alternating sram to flash parameter symbol condition value unit jedec standard min. max. ce recover time t ccr 0ns ce hold time t chold 3ns ce f t ccr t ccr ce1 s ce2s t ccr t ccr we t chold t chold
MB84VD23280EA-90/mb84vd23280ee-90 22 ? read only operations characteristics (flash) note: test conditionsC output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc f timing measurement reference level input: 0.5v cc f output: 0.5v cc f parameter symbol condition value (note) unit jedec standard min. max. read cycle time t avav t rc 90ns address to output delay t avqv t acc ce f = v il oe = v il 90ns chip enable to output delay t elqv t ce foe = v il 90ns output enable to output delay t glqv t oe 35ns chip enable to output high-z t ehqz t df 30ns output enable to output high-z t ghqz t df 30ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh 0ns reset pin low to read mode t ready 20s
MB84VD23280EA-90/mb84vd23280ee-90 23 ? read cycle (flash) we oe ce f t ce f t oe dq addresses stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc addresses stable high-z output valid t rh t df address address t rh t ce f t rp ce f
MB84VD23280EA-90/mb84vd23280ee-90 24 ? erase/program operations (flash) *1: this does not include the preprogramming time. *2: this timing is for sector group protection operation. *3: the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. a time-out or t tow from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command(s). *4: when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. parameter symbol value unit jedec standard min. typ. max. write cycle time t avav t wc 90 ns address setup time (we to addr.) t avwl t as 0ns address setup time to ce f low during toggle bit polling t aso 15 ns address hold time (we to addr.) t wlax t ah 45 ns address hold time from ce f or oe high during toggle bit polling t aht 0ns data setup time t dvwh t ds 35 ns data hold time t whdx t dh 0ns output enable hold time read t oeh 0ns toggle and data polling 10 ns ce f high during toggle bit polling t ceph 20 ns oe high during toggle bit polling t oeph 20 ns read recover time before write (oe to ce f) t ghel t ghel 0ns read recover time before write (oe to we )t ghwl t ghwl 0ns we setup time (ce f to we )t wlel t ws 0ns cef setup time (we to ce f) t elwl t cs 0ns we hold time (ce f to we )t ehwh t wh 0ns cef hold time (we to ce f) t wheh t ch 0ns write pulse width t wlwh t wp 35 ns ce f pulse width t eleh t cp 35 ns write pulse width high t whwl t wph 30 ns cef pulse width high t ehel t cph 30 ns word programming operation t whwh1 t whwh1 16 s sector erase operation * 1 t whwh2 t whwh2 1 s v cc f setup time t vcs 50 s voltage transition time * 2 t vlht 4s rise time to v id * 2 t vidr 500 ns rise time to v acc t vaccr 500 ns recover time from ry/by t rb 0ns reset pulse width t rp 500 ns delay time from embedded output enable t eoe 90 ns reset high level period before read t rh 200 ns program/erase valid to ry/by delay t busy 90 ns erase time-out time * 3 t tow 50 s erase suspend transition time * 4 t spd 20 s
MB84VD23280EA-90/mb84vd23280ee-90 25 ? write cycle (we control) (flash) t ch t wp t whwh1 t wc t ah ce f oe t rc dq t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce f t ds d out address notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
MB84VD23280EA-90/mb84vd23280ee-90 26 ? write cycle (ce f control) (flash) notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t cp t ds t whwh1 t wc t ah we oe dq t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd address
MB84VD23280EA-90/mb84vd23280ee-90 27 ? ac waveforms chip/sector erase operations (flash) address v cc f ce f oe dq we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase 30h *: sa is the sector address for sector erase. addresses = 555h for chip erase. note: these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
MB84VD23280EA-90/mb84vd23280ee-90 28 ? ac waveforms for data polling during embedded algorithm operations (flash) *: dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe ce f oe we dq 7 t df t ch t ce f dq 7 = valid data dq 7 * dq 6 to dq 0 = output flag t eoe dq 6 to dq 0 valid data high-z high-z dq 6 to dq 0 data in data in t busy ry/by t whwh1 or t whwh2
MB84VD23280EA-90/mb84vd23280ee-90 29 ? ac waveforms for toggle bit during embedded algorithm operations (flash) *: dq 6 stops toggling (the device has completed the embedded operation). address ry/by ce f we dq 6 /dq 2 oe t as t busy toggle t aht t aht t aso t oeh t oeh t oe data toggle data toggle data stop toggling data t ce f * output valid t dh t ceph t oeph
MB84VD23280EA-90/mb84vd23280ee-90 30 ? back-to-back read/write timing diagram (flash) ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce f t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note: this is an example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2.
MB84VD23280EA-90/mb84vd23280ee-90 31 ?ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) the rising edge of the last write pulse ce f ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb
MB84VD23280EA-90/mb84vd23280ee-90 32 ? temporary sector unprotection (flash) ? acceleration mode timing diagram (flash) v cc f v id reset v ih ce f we ry/by program or erase command sequence t vidr t vlht t vcs t vlht t vlht unprotection period 3v v cc f v acc wp /acc v cc ce f we ry/by t vaccr t vlht t vcs t vlht t vlht acceleration mode period
MB84VD23280EA-90/mb84vd23280ee-90 33 ? extended sector group protection (flash) spax: sector group address to be protected spay : next group sector address to be protected time-out : time-out window = 250 m s (min.) spay reset oe we ce f data a 1 v cc f a 6 , a 3 , a 2 , a 0 address spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc
MB84VD23280EA-90/mb84vd23280ee-90 34 ?read cycle (sram) parameter symbol value unit min. max. read cycle time t rc 70 ns address access time t aa 70ns chip enable (ce1 s) access time t co1 70ns chip enable (ce2s) access time t co2 70ns output enable access time t oe 35ns lb s, ub s to output valid t ba 70ns chip enable (ce1 s low and ce2s high) to output active t coe 5ns output enable low to output active t oee 0ns ub s, lb s enable low to output active t be 0ns chip enable (ce1 s high or ce2s low) to output high-z t od 25ns output enable high to output high-z t odo 25ns ub s, lb s output enable to output high-z t bd 25ns output data hold time t oh 10 ns
MB84VD23280EA-90/mb84vd23280ee-90 35 ?read cycle (sram) t rc t aa t oh t co1 t od t odo t oee t coe valid data out address ce1 s oe dq ce2s t coe t oe t co2 t od lb s, ub s t ba t bd t be note: we remains high for the read cycle.
MB84VD23280EA-90/mb84vd23280ee-90 36 ? write cycle (sram) parameter symbol value unit min. max. write cycle time t wc 70 ns write pulse width t wp 55 ns chip enable to end of write t cw 60 ns address valid to end of write t aw 60 ns ub s, lb s to end of write t bw 60 ns address setup time t as 0ns write recovery time t wr 0ns we low to output high-z t odw 25ns we high to output active t oew 0ns data setup time t ds 30 ns data hold time t dh 0ns
MB84VD23280EA-90/mb84vd23280ee-90 37 ? write cycle (note 3) (we control) (sram) t wc t as t wp t wr t cw t odw t oew t ds t dh valid data in address we ce1 s d out d in ce2s t cw notes: 1. if ce1 s goes low (or ce2s goes high) coincident with or after we goes low, the output will remain at high impedance. 2. if ce1 s goes high (or ce2s goes low) coincident with or before we goes high, the output will remain at high impedance. 3. if oe is high during the write cycle, the outputs will remain at high impedance. 4. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 1 note 4 note 2 note 4 t bw lb s, ub s t aw
MB84VD23280EA-90/mb84vd23280ee-90 38 ? write cycle (note 1) (ce 1s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in address we ce1 s d out d in ce2s t cw notes: 1. if oe is high during the write cycle, the outputs will remain at high impedance. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 2 lb s, ub s t bw t be t aw
MB84VD23280EA-90/mb84vd23280ee-90 39 ? write cycle (note 1) (ce2s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in address we ce1 s d out d in ce2s notes: 1. if oe is high during the write cycle, the outputs will remain at high impedance. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. note 2 t cw lb s, ub s t bw t be t aw
MB84VD23280EA-90/mb84vd23280ee-90 40 ? write cycle (note 1) (lb s, ub s control) (sram) t wc t ds t dh address lb s, ub s we d in notes: 1. if oe is high during the write cycle, the outputs will remain at high impedance. 2. because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wp ce2s t cw ce1 s t as t wr t bw t odw t coe d out t be valid data in note 2 t cw t aw
MB84VD23280EA-90/mb84vd23280ee-90 41 n n n n erase and programming performance (flash) n data retention characteristics (sram) note t rc : read cycle time ?ce1 s controlled data retention mode (note 1) parameter value unit remarks min. typ. max. sector erase time 1 10 s excludes programming time prior to erasure byte programming time 8 300 m s excludes system-level overhead word programming time 16 360 m s excludes system-level overhead chip programming time 200 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol value unit min. typ. max. data retention supply voltage v dh 1.5 3.3 v standby current v dh = 3.0 v i dds2 tbd15 m a chip deselect to data retention mode time t cdr 0ns recovery time t r t rc ns v cc s 2.7 v v ih gnd data retention mode see note 2 t cdr ce1 s v ccs C 0.2 v see note 2 t r v dh
MB84VD23280EA-90/mb84vd23280ee-90 42 ? ce2s controlled data retention mode (note 3) notes: 1. in ce1 s controlled data retention mode, input level of ce2s should be fixed vccs to vccsC0.2 v or vss to 0.2 v during data retention mode. other input and input/output pins can be used between C0.3 v to vccs+0.3 v. 2. when ce1 s is operating at the v ih min. level, the standby current is given by i sb1 s during the transition of v cc s from 3.3v to v ih min. level. 3. in ce2s controlled data retention mode, input and input/output pins can be used between C0.3 v to vccs+0.3v. n n n n pin capacitance note: test conditions ta = 25c, f = 1.0 mhz n handling of package please handle this package carefully since the sides of packages are right angle. n caution 1) the high voltage (v id ) can not apply to address pins and control pins except reset . therefore, it can not use autoselect and sector protect function by applying the high voltage (v id ) to specific pins. 2) for the sector protection, since the high voltage (v id ) can be applied to the reset , it can be protected the sector useing extended sector protect command. parameter symbol condition value unit min. typ. max. input capacitance c in v in = 0 ? tbd tbd pf output capacitance c out v out = 0 ? tbd tbd pf control pin capacitance c in2 v in = 0 ? tbd tbd pf wp /acc pin capacitance c in3 v in = 0 ? tbd tbd pf v cc s 2.7 v gnd data retention mode v ih v il ce2s t cdr t r 0.2 v v dh
MB84VD23280EA-90/mb84vd23280ee-90 43 n n n n ordering information mb84vd23280 ea -90 -pbs device number/description 64mega-bit (8m 16-bit or 4m 16-bit) dual operation flash memory 3.0v-only read, program, and erase 8mega-bit(1m 8-bit or 512k 16-bit) sram pa c k a g e t y p e pbs = 101-ball bga speed option see product selector guide device revision ea or ee
MB84VD23280EA-90/mb84vd23280ee-90 44 n n n n package dimension 101-pin plastic fbga (bga-101p-m01) c 2000 fujitsu limited b101001s-1c-1 12.00?.10(.472?004) 11.00?.10 (.433?004) index-mark area 0.10(.004) 0.39?.10 (.015?004) (stand off) .049 ?004 +.006 ?.10 +0.15 1.25 (mounting height) 0.80 (.031) 5.60(.220)ref 7.20(.283) 10.40(.409) 0.80 (.031) 5.60(.220) ref 8.80(.346) a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 101-.018 ?002 +.004 ?.05 +0.10 101-0.45 m 0.08(.003) dimensions in mm (inches).
MB84VD23280EA-90/mb84vd23280ee-90 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB84VD23280EA

	To Download MB84VD23280EA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .